Oscillator circuit

ABSTRACT

Present invention relates to an oscillator circuit comprising: resonator means ( 102 ) and, first and second emitter followers ( 116, 118 ) being symmetrically coupled to the resonator means and been connected to further emitter followers ( 120, 122 ) for providing capacitive loading.

Present invention relates to the field of oscillator circuits, and moreparticularly without limitation to the field of high frequencyoscillator circuits having oscillation frequencies in the GHz range.

A number of oscillator circuits operating in the GHz range are knownfrom the prior art. An oscillator circuit having a tuning range of 14GHz to 21.5 GHz is known from K. Ettinger, M. Bergmair, H. Pretl, W.Thomann, J. Fenk, R. Weigel, “An Integrated 20 GHz SiGe BipolarDifferential Oscillator with High Tuning Range”, Proceedings of the 2000Bipolar/BiCMOS Circuits and Technology Meeting (BCTM), Minneapolis,2000, pp. 161-163. ISBN 0-7803-6384-1. This oscillator circuit isrealised in SiGe bipolar technology and features a tank consisting ofon-chip strip line inductors and the parasitic capacitances of theoscillator transistors. An output buffer is inductively coupled to thetank. The oscillator core consists of an LC-tank and a cross-coupleddifferential amplifier. The cross-coupled pair provides the negativeresistance to compensate for the resistive losses of the tank. One ofthe disadvantages of this oscillator circuit is that the negativeresistance provided by the cross-coupled differential amplifier sufficesonly for frequencies up to 21.5 GHz.

A similar high frequency oscillator, which is realised in CMOStechnology is known from C. De Ranter and M. Steyaert, “A 0.25 μm CMOS17 GHzVCO” in ISSCC Digest of Technical Papers, pp. 370- 371, February2001. This oscillator circuit has also a LC-tank based voltagecontrolled oscillator having a cross-coupled transistor pair to coverthe power loss in the resistors and coil.

A further voltage controlled LC-oscillator with integrated high-Qinductor based on this design is known from

http://www.esscirc.org/esscirc2001/proceedings/data/169.pdf.

This circuit operates at a frequency of up to 10 GHz. Still anothervoltage controlled LC-tuned oscillator for 2.4 GHz applications is knownfrom

http://eesof.tm.agilent.com/pdf/nordic_vlsi.pdf.

Examples for other prior art oscillator circuits are shown in U.S. Pat.No. 4,810,976, U.S. Pat. No. 6,249,190 B1 and WO 02/065632A1. Againcross-coupled transistor pairs are used for un-damping the voltagecontrolled oscillator core.

It is a common disadvantage of prior art high frequency oscillators thatthe frequency range is limited by a cross-coupled transistor pair whichonly provides sufficiently negative resistance up to a certainfrequency. This frequency-limit depends on the technology used e.g. 25GHz in case of QUBiC4G.

Therefore a need exists to provide an improved oscillator circuit, whichenables to increase the prior art frequency-limit. The invention isdefined by the independent claim. Dependent claims define advantageousembodiments.

The present invention provides for an oscillator circuit having firstand second emitter followers being symmetrically coupled to a resonator.The emitter followers have a capacitive load. The capacitive loading ofthe transistors of the emitter followers results in a negative realvalue of the input impedance, which has the effect of un-damping theresonator. Hence, usage of a cross-coupled transistor pair is avoided.

Preferably the resonator is realized as an LC resonator. For example theresonator can be realized by means of an inductor and a varactor with atuning voltage for frequency tuning. In series with this varactor, ahigh value capacitor for low series resistance is added. By doing so,the anode of the varactor is DC grounded via a high-ohmic seriesresistance and the cathode is tuneable from zero volt to supply voltageVCC. The bottom-plate of the varactor, which parasitics are high, iscommon-mode. This topology has the largest possible tuning range withinthe supply voltage. The varactor is biased between zero bias to reversebias.

In accordance with a preferred embodiment of the invention the resonatorcircuit is realized as a common cathode tank circuit. Alternatively theresonator circuit is a common anode tank circuit.

In accordance with a preferred embodiment of the invention, thecapacitive loading of the first and second emitter followers is providedby a second emitter follower pair. This way two pairs of cascadedemitter followers are provided.

Alternatively or in addition a capacitor is inter-coupled between thefirst and second emitter followers to provide the capacitive load.

In accordance with a further preferred embodiment of the invention, alevel shifter is coupled between the supply voltage and the resonator.The level shifter can be realized by one or more diodes. A diode acts asa level shift as it enables a larger signal swing across the resonatorbefore the emitter followers' base-collector junction starts to clampthe signal on the resonator.

The present invention is particularly advantageous in that it enables torealize a high-frequency oscillator circuit other than by means of across-coupled transistor pair. In particular, the present inventionenables to realize an oscillator circuit having a low- and a highfrequency-limit, depending on the technology used e.g. above 20 GHz andup to 40 GHz in case of QUBiC4G. This is particularly advantageous forapplications like phase-locked loops, up-converters, down-converters,mixers and signal generators to name a few.

Other advantages obtained using the present invention are as follows:

the phase noise improves since noise contributions from thecross-coupled transistor pair disappear;

the required chip area is reduced;

the high signal swing at the output of the oscillator circuit is enableddue to the high capacitive load of the emitter followers;

the tuning range of the oscillator circuit increases significantly asless parasitics are connected through the resonator circuit.

In the following preferred embodiments of the invention will bedescribed in greater detail by making reference to the drawings inwhich:

FIG. 1 is a block diagram of a first embodiment where the capacitiveload is provided by a second emitter follower pair,

FIG. 2 is a block diagram of a second embodiment of the invention withan additional capacitor coupled between the emitter followers,

FIG. 3 is illustrative of a parallel equivalent input impedance of theoutput buffer,

FIG. 4 is illustrative of a parallel equivalent RC-circuit of theresonator (inductor and varactor), and

FIG. 5 shows transient results in the tuning range from 39.4 GHz up to43.1 GHz, and

FIG. 6 shows the phase noise results at 40 GHz.

FIG. 7 shows a block diagram of a quadrature oscillator;

FIG. 8 shows a quadrature oscillator using a parallel coupling,according to an embodiment of the invention; and

FIG. 9 shows a quadrature oscillator using a serial coupling, accordingto another embodiment of the invention.

FIG. 1 shows an oscillator circuit 100 having a resonator 102. In theexample considered here, the resonator 102 has an inductor 104 which issymmetrically coupled to a current source 106 providing a current Id;further inductor 104 is symmetrically coupled to the supply voltage.Resonator 102 has varactor 108 with a control terminal 110 to apply atuning voltage Vtune for frequency tuning. Capacitors 112 are coupled inseries with varactor 108. Preferably capacitors 112 have a high valueand thus a low series resistance. Hence, the anode of the varactor 108is DC grounded via a high-ohmic series resistances 114 and the cathode,i.e. the control terminal 110, is tuneable from zero volt to supplyvoltage. The bottom-plate of the varactor is common-mode. This topologyallows the largest possible tuning range within the supply voltage. Theresonator 110 is of the common cathode type such that the anodes of theresonator 102 are coupled to emitter followers 116 and 118,respectively. Emitter followers 116 and 118 have a symmetric design andboth comprise a transistor T1 and a current source Ief1. The bases ofthe transistors T1 of the emitter followers 116 and 118 are coupled tothe anodes of the resonator 102. Capacitive loading of the emitterfollowers 116 and 118 is provided by emitter followers 120 and 122.Again emitter followers 120 and 122 are designed symmetrically and eachhave a transistor T2 and current source Ief2. The base of transistor T2of emitter follower 120 is coupled to the emitter of transistor T1 ofemitter follower 116; likewise the base of transistor T2 of emitterfollower 122 is coupled to the emitter of transistor T1 of emitterfollower 118. The capacitive loading of the transistors T1 provided bythe emitter followers 120 and 122 result in a negative real part of theinput impedance seen from the resonator 102. This negative real part ofthe input impedance is used to un-damp the resonator 102. Resistors Rsare used to realize single-ended output impedances to provide the outputterminals OUT+ and OUT−. For example each one of the resistors Rs has animpedance of 50 ohm. The outputs OUT+ and OUT− are coupled by means ofcapacitors Cac to output loads 124 which preferably are also 50 ohm.

FIG. 2 is a block diagram of an alternative embodiment. Like elements inFIGS. 1 and 2 are designated by the same reference numerals. Like in theembodiment of FIG. 1 the resonator 102 of the embodiment of FIG. 2 iscoupled to cascaded emitter followers 116, 120 and 118,122. Emitterfollower 120 provides a capacitive load for emitter follower 116;likewise emitter follower 122 provides a capacitive load to emitterfollower 118. In the embodiments considered here, capacitor C1 is addedto increase the capacitive load of the emitter followers 116 and 118.Capacitor C1 is connected between the emitters of transistors T1. If thecapacitance of capacitor C1 is sufficiently large it is also possible toleave out the emitter followers 120 and 122 and to directly connect theresistors Rs to the emitters of transistors T1. Further there is a levelshifter circuit 126 which is symmetrically coupled between the supplyvoltage and the resonator 102. Level shifter circuit 126 has a diode D1and a capacitor Cx which is connected in parallel to the diode D1. DiodeD1 acts as a level shift and is used to allow a large up to two diodessignal swing across the resonator 102 before the base-collector junctionof the transistors T1 starts to clamp the signal on the resonator 102.Additional diodes can be added in series with diode D1 to furtherincrease the maximum attainable signal swing. The additional noise ofdiode D1 is filtered by capacitor Cx, while its noise may also bereduced by increasing the DC current through diode D1 using currentsource Id.

The negative real part of the input impedance of the output buffer,which is due to the capacitive loading of the emitter followers 116 and118 has a slope of 1/ƒ²):$R_{P} = {\frac{1}{{real}\left( Y_{i\quad n} \right)} = \frac{- \omega_{r}}{\omega^{2}C_{l}}}$

With C₁ the input capacitance of the emitter followers 120 and 122 andR_(p) the differential parallel input resistance seen from the resonator102. Because this resistance must be lower in absolute value than thepositive resistance from the resonator 102 to start oscillation, thistopology is particularly useful above frequencies where the negativeresistance is low enough. In prior art tank circuits usually thequality-factor lowers at increasing frequency due to the fixed seriesresistance of the varactor and the increasing series resistance of theinductor due to skin-effect. Because the parallel resistance of theresonator 102 has a less steep slope than 1//(ƒ²), the new topology isuseful at higher frequencies, depending on the technology used e.g.above 20 GHz and up to 40 GHz in case of QUBiC4G. The parallelequivalent input impedance of the output buffer is shown in FIG. 3. At40 GHz, the equivalent RC-circuit is −504 Ω in parallel with 21 fFenabling a practical implementation of a 40 GHz VCO in a Philips QUBiC4Gprocess. At 56 GHz, the resistance is not negative anymore, placing anew frequency limit at 56 GHz for an LC-VCO in QUBiC4G with this newtopology.

FIG. 4 shows the parallel equivalent RC-circuit of the practicalimplementation of resonator 102 in QUBiC4G. The negative resistance of−504 Ω in parallel to this resonator 102 (from the buffer) is adequateto start oscillation at tuning voltages above 0.5 V (where the positiveparallel resistance from the tank is +526 Ω). The transient results ofthe LC-VCO with the new topology of FIG. 2 are shown in FIG. 5. Thephase noise results are shown in FIG. 6. The tuning range is from 39.4GHz up to 43.1 GHz (tuning from 0.5 to 3.5 V). The phase noise isworst-case (at 0.5 V tuning voltage) −92 dBc/Hz at 4 MHz. The circuitprinciples can also be implemented using PNP transistors instead of NPNtransistors. The output buffer can be implemented as class-A/B if bothNPN and PNP transistors are available. Also NMOS and/or PMOS transistorsmay be used, as long as the first stage of the buffer, i.e. emitterfollowers 116, 118, provides 90 degrees phase shift and remains (partly)capacitively loaded.

The topologies of FIGS. 1 and 2 have a number of advantages, some ofwhich are summarized below:

Un-damping via the output buffer, with a given tank-circuit, alwaysresults in an increase in tuning range and a higher oscillationfrequency. These two advantages are due to the reduced capacitiveloading to the resonator when comparing a cross-coupled bipolar circuitin a prior art topology versus an output buffer comprising two emitterfollowers in cascade;

The invention enables to avoid the cross-coupled bipolar pair(−2/g_(m)). This was the limiting factor in frequency, because thenegative resistance has a certain frequency-limit where the resistancebecomes positive. This frequency-limit is lower than for the topology ofFIGS. 1 and 2;

For a fixed tank-circuit, the phase noise result is always better forthe new topology, comparing to the prior art topology, because noisesources from the cross-coupled pair are not present anymore;

Because the output buffer of FIGS. 1 and 2 comprises two emitterfollowers in cascade, there is no signal swing in the collector, whichallows a higher swing. In prior art designs, a degenerated differentialpair is usually added as a first stage in the buffer to have ahigh-ohmic resistance in parallel to the tank. For that stage, theattenuation is high, resulting in a lower voltage swing for anequivalent tank;

Omitting the cross-coupled pair reduces the power dissipation of theVCO.

FIG. 7 shows a block diagram of a quadrature oscillator. Quadraturesignal generation can be implemented in several ways. For low phasenoise, usually resonator (LC)-type VCOs are used as building block Usingtwo LC-VCO cores plus some means to couple them, quadrature signalgeneration is implemented. In FIG. 7, this principle for IQ eneration isshown. The two VCO cores are substantially identical. Both are assumedto generate a differential output signal. One cross coupling in the loopimplements 180° phase shift; each of the cores provides 90° phase shift.Several implementations for LC-type VCO cores are known. The core usesan LC tank circuit as previously described.

FIG. 8 shows a quadrature oscillator using a parallel coupling,according to an embodiment of the invention the first oscillator circuitcomprises a first pair of transistors T_(c1), T_(c2) and the secondoscillator circuit comprises a second pair of transistorsT_(c1)′,T_(c2)′ coupled to the respective third emitter follower 120;120′ and the respective fourth emitter follower 122; 122′. Collectors ofthe first pair of transistors T_(c1)′, T_(c2) are coupled to the tankcircuit included in the second oscillator circuit and collectors of thesecond pair of transistors T_(c1)′, T_(c2)′ are crossed coupled to thetank circuit of the first oscillator circuit. A drawback of the parallelimplementation is the increased tank load due to the connection from theoupling transistors T_(c1), T_(c2) and T_(c1)′, T_(c2)′ to the LC-tankIn the figure, the bases of the coupling transistors may also be coupledto the emitters of 120, 122; 120′, 122′.

FIG. 9 shows a quadrature oscillator using a serial coupling, accordingto another embodiment of the invention. The first oscillator circuitcomprises a first pair of transistors T_(c1), T_(c2) and the secondoscillator circuit comprises a second pair of transistors T_(c1)′,T_(c2)′ coupled to the third emitter follower 120, 122 and respectivefourth emitter follower 120′, 122′. Collectors of the first pair oftransistors T_(c1), T_(c2) are coupled to respective bases of the secondpair of transistors T_(c1)′, T_(c2)′. Collectors of the second pair oftransistors T_(c1)′, T_(c2)′ are crossed-coupled to respective bases ofthe first pair of transistors T_(c1), T_(c2). The series implementationfor a quadrature oscillator is preferred, because the loading of theLC-tank is reduced. Besides, the total bias current does not need to beincreased, because of the series connection of the coupling transistors.The coupling transistors T_(c1), T_(c2); T_(c1)′, Tc_(c2)′ share thebias current Ief2 of the respective emitter followers 120, 122; 120′,122′.

The embodiments refer to implementations in bipolar technology but theinventive concept may be applied mutatis-mutandis to other technologiesas e.g. GaAs, SiGe, CMOS, etc. As a consequence the terminals base,emitter and collector correspond to gate, source, drain, respectively.

It is remarked that the scope of protection of the invention is notrestricted to the embodiments described herein. Neither is the scope ofprotection of the invention restricted by the reference numerals in theclaims. The word ‘comprising’ does not exclude other parts than thosementioned in the claims. The word ‘a(n)’ preceding an element does notexclude a plurality of those elements. Means forming part of theinvention may both be implemented in the form of dedicated hardware orin the form of a programmed purpose processor. The invention resides ineach new feature or combination of features.

REFERENCE NUMERALS

-   100 oscillator circuit-   102 resonator-   104 inductor-   106 current source-   108 varactor-   110 control terminal-   112 capacitor-   114 resistance-   116 emitter follower-   118 emitter follower-   120 emitter follower-   122 emitter follower-   124 output load-   126 level shifter circuit

1. An oscillator circuit comprising: resonator means (102) and, firstand second emitter followers (116, 118) being symmetrically coupled tothe resonator means and having a capacitive load (120, 122, C1).
 2. Theoscillator circuit of claim 1, the resonator being an LC resonator. 3.The oscillator circuit of claim 1, the resonator being a voltagecontrolled resonator.
 4. The oscillator circuit of claim 3, theresonator having a varactor (108) with a control voltage input (110) forfrequency tuning.
 5. The oscillator circuit of claim 4, a capacitor(112) being coupled to the varactor in series and a bottom-plate of thevaractor being common-mode.
 6. The oscillator circuit of claim 1, theresonator circuit being a common cathode tank circuit.
 7. The oscillatorcircuit of claim 1, the resonator circuit being a common anode tankcircuit.
 8. The oscillator circuit of claim 7, further comprising athird emitter follower (120) and a fourth emitter follower (122), thefirst and the third emitter followers being cascaded and the second andthe fourth emitter followers being cascaded.
 9. The oscillator circuitof claim 1, a capacitor (C1) being coupled between the first and secondemitter followers (116, 118).
 10. The oscillator circuit of claim 1,further comprising level shifter means (126) coupled between a supplyvoltage and the resonator means.
 11. The oscillator circuit of claim 10,the level shifter means comprising at least one diode (D1).
 12. Aquadrature oscillator comprising a first oscillator circuit as claimedin claim 8 crossed-coupled to a second oscillator circuit claim
 8. 13. Aquadrature oscillator as claimed in claim 12, wherein the firstoscillator circuit comprises a first pair of transistors (T_(c1),T_(c2)) and the second oscillator circuit comprises a second pair oftransistors (T_(c1)′, T_(c2)′) coupled to the respective third emitterfollower (120; 120′) and the respective fourth emitter follower (122;122′), collectors of the first pair of transistors (T_(c1), T_(c2))being coupled to the tank circuit included in the second oscillatorcircuit and collectors of the second pair of transistors (T_(c1)′,T_(c2)′) being crossed coupled to the tank circuit of the firstoscillator circuit.
 14. A quadrature oscillator as claimed in claim 12,wherein the first oscillator circuit comprises a first pair oftransistors (T_(c1)′, T_(c2)′) and the second oscillator circuitcomprises a second pair of transistors (T_(c1)′, T_(c2)′) coupled to thethird emitter follower (120, 122) and respective fourth emitter follower(120′, 122′), collectors of the first pair of transistors (T_(c1),T_(c2)) being coupled to bases of the second pair of transistors(T_(c1)′, T_(c2)′) collectors of the second pair of transistors(T_(c1)′, T_(c2)′) being crossed-coupled to bases of the first pair oftransistors (T_(c1), T_(c2)).
 15. An electronic device such as aphase-locked loop, an up-converter, down-converter, mixer or signalgenerator comprising an oscillator circuit of claim 1.